Design of low power, high speed full adder using PTL-TG Hybrid style

Full adders are essentially used as a building block in all arithmetic, DSP and microprocessor applications. In this paper, a 15 transistor hybrid PTL-TG full adder circuit is proposed. The main objective is to provide high speed, low power, full swing operation with good drivability. The choice of logic design affects the circuit performance. The delay time depends on the number of transistors used and design complexity. The power consumption depends on size of transistors. The proposed adder consists of a hybrid circuit using pass transistors, CMOS gates and transmission gates. The design is simulated using TANNER EDA v14 simulation tool. The performance is measured in terms of power, delay and Power Delay Product (PDP). The analysis has been done using 180 nm CMOS technology. Performance has been compared for variation of Supply voltage [1.2V-1.8V] at 200MHz frequency with 1fF load conditions. The reduction in power and delay is necessary for applications of full adder in low power, portable devices. The proposed hybrid adder shows better performance as compared to existing DPL and SR-CPL adders and it shows significantly low Power, delay and PDP. The proposed hybrid adder shows fully restored output logic levels. Utilization of a hybrid technique allows us to achieve the individual advantages of pass transistors and transmission gates and avoid the limitations of both designs. A 2 bit ripple carry adder is designed using proposed adder.